A memory device may include a deep sleep or light sleep mode, which is an operating mode in which the memory banks of the memory device are in a reduced power state or altogether completely shut off. The use of a sleep mode reduces the amount of electrical power consumed in comparison to an awake or normal operating mode of the memory device.
FIG. 1 illustrates a prior art block diagram of a memory device with some memory instances in a deep-sleep mode. A memory device 10 comprises memory instances 8 and 12. The memory instances 8 are in a deep-sleep mode and the memory instances 12 are in a normal active mode (also referred to as a functional mode). When some or all of the memory instances 8 are woken up, there is a pull down effect on the power supply to the memory device.
For instance, when the memory instances 8 are switched to an active state, the internal core voltage supplies for these instances 8 are woken up by charging them. This causes a current surge on the power supply, which can be very large. The current from the power supply can significantly droop due to the instantaneous current consumed to charge the memory instances. The power supply can droop low enough that the currently active memory instances 12 may fail.
Furthermore, there is typically a switch that gates the power supply to each of the memory instances. When the switch is opened (meaning the respective instance is not being powered), the internal core voltage supply of the respective instance drains to ground due to voltage leakage. Eventually, the bitcells of the memory instance will lose its contents since the internal power will drop below a minimum voltage to keep the contents stored in the bitcells. In order to gain power savings, power gating or a light sleep mode is applied in which the internal core voltage supply is intentionally dropped a little in voltage (e.g., dropped about 100 mV).
FIG. 2 illustrates a graph of a power supply that is pulled down by memory instances being woken up. The graph of a power supply has two voltage rails one set at a voltage VCS and one set at ground. When the memory instances are woken up, the power surge will cause the VCS and ground voltages to droop below a minimum operating voltage range Vmin Fail. The memory instances must be operated at a range greater than the minimum operating voltage range to perform reliably. Due to the power source drooping below the minimum operating voltage range, the already active memory instances may undesirably fail and lose its stored data.
In order to combat such issues, prior art has developed various methods for preventing active memory failures. In one method, the current surge from waking the memory banks is reduced by having an inverter delay chain that charges one bank first, and then a next bank after a preset amount of time has elapsed. The delay can be programmed into the inverter delay chain. In other words, the banks are turned on in a stagger manner using delay elements to provide time delays for such staggering. However, a drawback of this method is that it's slow. Additionally, the performance of the inverter delay chain elements can undesirably change the wake-up current profile due to the process characteristics of the device.
Another prior art method provides for the charging of bit lines of a memory bank for waking up that memory bank. First, the bit lines are allowed to discharge to ground. Next, the bit lines are powered up sequentially using the power supply. The power supply droop is thereby minimized by slowly charging up each of the bit lines one at a time for each of the memory banks. However, in actual application this is not useful since there are a tremendous number of bit lines in each of the memory banks. The amount of circuit overhead alone to individually charge each one of the bit lines is untenable; not to mention the amount of time needed to sequentially charge each bit line is very long.
Therefore, it is desirable to provide new methods, circuits, and systems for waking up memory banks of a memory device to prevent a steep drop in the current of a power supply for the memory device.